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19-2108; Rev 1; 8/03
KIT ATION EVALU BLE AVAILA
W-CDMA Upconverter and PA Driver with Power Control
General Description Features
o +6dBm Output Power with -46dBc ACPR o Ultra-Miniature UCSP Package o Upconverter Gain-Control Range: 35dB o Automatic Dynamic Current Control o 12mA Quiescent Supply Current o On-Chip LO Buffer with Disable o Low Out-of-Band Noise Power in RX Band: -144dBm/Hz at +6dBm POUT o No Interstage TX SAW Bandpass Filter Required
MAX2383
The MAX2383 upconverter and PA driver IC is designed for emerging ARIB (Japan) and ETSI-UMTS (Europe) W-CDMA applications. The IC includes an upconversion mixer with variable gain control, an LO buffer, and a variable-gain PA driver for output power control. The MAX2383 is designed to support the IMT-2000 frequency band. It includes a differential IF input port, an LO input port, and PA driver input/output ports. The upconverter mixer incorporates an AGC with over 30dB of gain control. The IC provides automatic throttle-back of PA driver and mixer current as output power is reduced. The main signal path and the LO buffer can be shutdown independently. The on-chip LO buffer can be kept ON while the main transmitter path is being turned on and off to minimize VCO pulling during TX gated-transmission. The MAX2383 is specified for +2.7V to +3.0V single supply and is housed in an ultra-miniature 3 x 4 UCSPTM package for optimum cost- and space-reduction and for best RF performance. The IC is targeted for the 2270MHz to 2580MHz LO frequency range. It is fabricated using an advanced high-frequency bipolar process. The mixer and PA driver linearity have been optimized to provide excellent RF performance in the 1920MHz to 1980MHz band, while drawing minimal current. The mixer's performance is optimized for a -10dBm 3dB LO drive at the LO buffer input port. The LO port can be configured to be driven either singleended or differentially. The MAX2383 achieves excellent noise and image suppression without the use of an interstage TX SAW bandpass filter, thereby saving valuable board space, cost, and supply current. For LNA and downconverter mixer companion ICs, see the MAX2387/MAX2388/MAX2389 data sheet.
Ordering Information
PART MAX2383EBC-T TEMP RANGE -40C to +85C PIN-PACKAGE 3 x 4 UCSP
ACTUAL SIZE UCSP 2mm 1.5mm
Block Diagram
TOP VIEW
Applications
Japanese 3G Cellular Phones (ARIB) European 3G Cellular Phones (UMTS) Chinese 3G Cellular Phones (TD-SCDMA) PCS Phones
Pin Configuration appears at end of data sheet. Typical Operating Circuit appears at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc.
LO+ / LO_EN
A1
VCC A2
DROUT A3
GND A4 PA DRVR
MAX2383
LO-/ SHDN B1 GC B3
B4 DRIN
C1 IFIN-
C2 IFIN+
C3 RFOUT
C4 GND
________________________________________________________________ Maxim Integrated Products
1
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W-CDMA Upconverter and PA Driver with Power Control MAX2383
ABSOLUTE MAXIMUM RATINGS
VCC, RFOUT to GND ..............................................-0.3V to +6.0V AC Signals ................................................................+1.0V Peak SHDN, LO_EN, VGC to GND ......................-0.3V to (VCC + 0.3V) Digital Input Current ....................................................... 10mA Continuous Power Dissipation (TA = +70C) 12-Pin UCSP (derate 80mW/C above +70C) ........ 628mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +160C Lead Temperature (Bump Reflow) ..................................+235C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.0V, SHDN = +1.5V, TA = -40C to +85C. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Voltage Operating Supply Current Shutdown Supply Current LO Buffer Current Digital Input Logic High Digital Input Logic Low Input Logic High Current Input Logic Low Current Recommended Gain-Control Voltage Gain-Control Input Bias Current SYMBOL VCC ICC ICC ICC VIH VIL IIH IIL VGC IGC 0.5V VGC 2.0V -1 0.5 -5 2.0 5 PDROUT = +6dBm, VGC = 2.0V PIF -35dBm, VGC = 1.4V SHDN = 0.5V, LO_EN = 0.5V, VGC = 0.5V SHDN = 0.5V, LO_EN = 1.5V, VGC = 2V 1.5 0 CONDITIONS MIN 2.7 TYP 2.85 34 12 0.5 6 MAX 3.0 44 20 10 8 VCC 0.5 1 UNITS V mA A mA V V A A V A
AC ELECTRICAL CHARACTERISTICS
(MAX2383 EV Kit; VCC = +2.7V to +3.0V; SHDN = LO_EN = +1.5V; IF source impedance = 400 (differential), IF input level = -16dBm (differential); LO input level = -10dBm, differential LO drive from 150 source impedance; mixer upconverter and PA driver are cascaded directly through an interstage matching network; DROUT drives a 50 load impedance; VGC = 2.0V; fIF = 380MHz, fRF = 1920MHz to 1980MHz, fLO = 2300MHz to 2360MHz; TA = -40C to +85C. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER IF Frequency RF Frequency Range LO Frequency Range Output Power (meets ACPR specifications) Power Gain SYMBOL fIF fRF fLO PDROUT GP (Note 2) (Note 2) High-side LO case (Note 2) VGC = 2.0V VGC = 2.0V 3 limit 6 limit 4.4 3.8 17 1920 2270-2580 +6 +6 19.5 CONDITIONS MIN TYP 200-600 1980 MAX UNITS MHz MHz MHz dBm dB
CASCADED PERFORMANCE (measured from IF input to DROUT (PA driver output))
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W-CDMA Upconverter and PA Driver with Power Control
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2383 EV Kit; VCC = +2.7V to +3.0V; SHDN = LO_EN = +1.5V; IF source impedance = 400 (differential), IF input level = -16dBm (differential); LO input level = -10dBm, differential LO drive from 150 source impedance; mixer upconverter and PA driver are cascaded directly through an interstage matching network; DROUT drives a 50 load impedance; VGC = 2.0V; fIF = 380MHz, fRF = 1920MHz to 1980MHz, fLO = 2300MHz to 2360MHz; TA = -40C to +85C. Typical values are at VCC = +2.85V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Gain-Control Range Adjacent Channel Power Ratio Alternate Channel Power Ratio Out-of-Band Noise Power in RX Band TX In-Band Noise Power TX In-Band Noise Power Recommended LO Input Level PLO ACPR1 ACPR2 SYMBOL CONDITIONS VGC = 0.5V to 2.0V, PIF -35dBm VGC = 2.0V (5MHz offset / 3.84MHz BW) VGC = 2.0V (10MHz offset / 3.84MHz BW) VGC = 2.0V, PDROUT = +6dBm (TX: 1980MHz; RX: 2110MHz) VGC = 2.0V, PDROUT = +6dBm VGC = 0.5V, PDROUT = -35dBm Differential -13 -144 -139 -147 -10 -7 MIN 25 TYP 35 -46 -56 -140 -135 MAX UNITS dB dBc dBc dBm/ Hz dBm/ Hz dBm/ Hz dBm
MAX2383
Note 1: Minimum and maximum values are guaranteed by design and characterization over temperature and supply voltages. Note 2: Operation outside this frequency range is possible, but has not been verified.
Typical Operating Characteristics
(MAX2383 EV Kit; VCC = +2.85V; SHDN = LO_EN = VCC, VGC = 2.0V; IF source impedance = 400 (differential), IF input level = -16dBm (differential); LO input level = -10dBm, differential LO drive from 150 source impedance; mixer upconverter and PA driver are cascaded through an interstage matching network; DROUT drives a 50 load impedance; fIF = 380MHz, fRF = 1950 MHz, fLO = 2330MHz; TA = +25C.)
TOTAL SUPPLY CURRENT vs. GAIN-CONTROL VOLTAGE
MAX2383 toc01
TOTAL SUPPLY CURRENT vs. TEMPERATURE
MAX2383 toc02
CONVERSION POWER GAIN vs. GAIN-CONTROL VOLTAGE
20 CONVERSION POWER GAIN (dB) 15 10 5 0 -5 -10 -15 -20 -25 TA = +85C TA = +25C TA = -40C
MAX2383 toc03
37 34 TOTAL SUPPLY CURRENT (mA) 31 28 25 22 19 16 13 10 0 0.5 1.0 1.5 2.0 TA = -40C TA = +85C TA = +25C
40 35 TOTAL SUPPLY CURRENT (mA) 30 SHDN = HIGH, LO_EN = HIGH 25 20 15 10 5 0 SHDN = LOW, LO_EN = HIGH
25
2.5
-40
-15
10
35
60
85
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VGC (V)
VGC (V)
TEMPERATURE (C)
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W-CDMA Upconverter and PA Driver with Power Control MAX2383
Typical Operating Characteristics (continued)
(MAX2383 EV Kit; VCC = +2.85V; SHDN = LO_EN = VCC, VGC = 2.0V; IF source impedance = 400 (differential), IF input level = -16dBm (differential); LO input level = -10dBm, differential LO drive from 150 source impedance; mixer upconverter and PA driver are cascaded through an interstage matching network; DROUT drives a 50 load impedance; fIF = 380MHz, fRF = 1950 MHz, fLO = 2330MHz; TA = +25C.)
CONVERSION POWER GAIN vs. RF FREQUENCY
MAX2383 toc04
CONVERSION POWER GAIN vs. LO INPUT LEVEL
MAX2383 toc05
PDROUT vs. TEMPERATURE
ACPR = -46dBc 6.5 6.0 5.5 5.0 4.5 4.0 -40 -15 10 35 60 85 TEMPERATURE (C) ACPR = -49dBc
MAX2383 toc06
21.0 CONVERSION POWER GAIN (dB) 20.5 20.0 19.5 19.0 18.5 18.0 1920
21.0 CONVERSION POWER GAIN (dB) 20.5 20.0 19.5 19.0 18.5 18.0
7.0
1930
1940
1950
1960
1970
1980
-13
-12
-11
-10 PLOIN (dBm)
-9
-8
-7
RF FREQUENCY (MHz)
PDROUT (dBm)
ACPR1 AND ACPR2 vs. PDROUT
MAX2383 toc07
RX BAND NOISE POWER vs. TEMPERATURE
MAX2383 toc08
INBAND NOISE POWER vs. GAIN-CONTROL VOLTAGE
MAX2383 toc09
-30 -35 ACPR AND ACPR2 (dBc) -40 -45 -50 -55 -60 -65 -70 -75 -5 -3 -1 1 3 5 7 9 ACPR1 AT VGC = 1.5V ACPR2 AT VGC = 1.7V ACPR2 AT VGC = 2V ACPR1 AT VGC = 2V ACPR1 AT VGC = 1.7V
-144 -145 NOISE POWER (dBm/Hz) -146 -147 -148 -149 -150 TX: 1980MHz, NOISE MEASURED AT 2110MHz PDROUT = +6dBm
-136 -138 NOISE POWER (dBm/Hz) -140 -142 -144 -146 -148 -150 TX : 1980MHz, NOISE MEASURED AT 1960MHz 0 0.5 1.0 VGC (V) 1.5
11
-40
-15
10
35
60
85
2.0
PDROUT (dBm)
TEMPERATURE (C)
LO LEAKAGE vs. GAIN-CONTROL VOLTAGE
MAX2383 toc10
IMAGE SUPPRESSION vs. RF FREQUENCY
-22 IMAGE SUPPRESSION (dBc) -24 -26 -28 -30 -32 -34 -36
MAX2383 toc11
OUTPUT RETURN LOSS vs. RF FREQUENCY
MAX2383 toc12
-20 -25 LO LEAKAGE (dBm) -30 -35 PLO = -7dBm -40 -45 -50 0.5 1.0 VGC (V) 1.5 PLO = -10dBm
-20
-8 -10 VGC = 1.4V -12 -14 -16 -18 -20 1920 VGC = 1.7V VGC = 2V
2.0
OUTPUT RETURN LOSS (dB)
1920
1930
1940
1950
1960
1970
1980
1930
1940
1950
1960
1970
1980
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
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W-CDMA Upconverter and PA Driver with Power Control
Pin Description
PIN A1+ A2 A3 A4 B1 B3 B4 C1 C2 C3 C4 NAME LO_EN /LO+ VCC DROUT GND SHDN/ LOGC DRIN IFINIFIN+ RFOUT GND FUNCTION LO Buffer Enable Pin. When LOW, the LO buffer shuts off. Also noninverting input for LO port. It can be ACcoupled to GND, when the LO is driven single-ended. Power-Supply Pin. Bypass with a 330pF capacitor to GND as close to the pin as possible. PA Driver Output Pin. Externally matched to 50. Ground Reference for RF Shutdown Pin. When LOW, the entire part shuts off, except for LO buffer. Also inverting input for LO port. It can be AC-coupled to GND, when the LO is driven single-ended. Power Control Input Pin (0.5V to 2.0V for control voltage) PA Driver Input Pin (interstage node). Can be externally matched to 50. Inverting IF Input (400 differential nominal impedance between IFIN+ and IFIN-) Noninverting IF Input (400 differential nominal impedance between IFIN+ and IFIN-) Upconverter Output Port (interstage node). Can be externally matched to 50. Ground Reference for RF
MAX2383
Detailed Description
Variable-Gain Mixer
The MAX2383 contains a double-balanced Gilbert cell mixer merged with a gain-control circuit, followed by a mixer buffer. The mixer is driven differentially at its IF ports. The LO input for the mixer is conditioned through a low-noise, inductively loaded buffer. The mixer differential output is driven through an on-chip balun into a single-ended common emitter amplifier, which drives the output pin (RFOUT). The mixer buffer is a singleended in/out common emitter stage with inductive degeneration and an external inductive load. Additionally, these circuits are biased from "VCS" generators, designed to produce a low-noise constant degeneration voltage at the user's current source. These bias circuits also provide the control required to selectively power-down the circuit and also provide for gain control and current throttle-back.
turn off the whole IC when both pins are pulled LOW. LO_EN helps reduce VCO pulling in gated-transmission mode by providing means to keep the LO buffer on while the upconverter and driver turn on and off. To avoid loading of the LO buffer, connect a 10k isolation resistor between the LO_EN/LO+ pin and the LO_EN logic input, and a 10k isolation resistor between the SHDN/LO- pin and the SHDN logic input.
Differential IF Inputs
The MAX2383 has a differential IF input port for interfacing to differential IF filters. The IF pins should be ACcoupled to the IF ports. The typical IF frequency is 380MHz, but the device can operate from 200MHz to 600MHz. The differential impedance between the two IF inputs is approximately 400 in parallel with 1.0pF.
Interstage Matching
The mixer buffer drives the following PA driver through an interstage matching network connected between the mixer's RFOUT pin and the PA driver's input pin (DRIN). This off-chip matching network, which consists of two series inductors and a parallel capacitor, is designed to achieve better than 25dBc image suppression with no current consumption penalty. The quality factor of this off-chip resonant circuit determines the image suppression level and usable bandwidth from the point of view of passband gain flatness.
PA Driver
The PA buffer is a single-ended in/out common emitter stage with inductive degeneration and an external inductive load.
Applications Information
LO Buffer Inputs
The external LO is interfaced either differentially or single-ended to the differential LO buffer. Those two pins also function as the control inputs for the device. Hence, they are DC-coupled to the chip-control circuitry, and AC-coupled to the LO port. SHDN and LO_EN
PA Driver Output
The PA driver output, DROUT, is an open-collector output that requires an external inductor to VCC for proper biasing. The output matching components are chosen
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W-CDMA Upconverter and PA Driver with Power Control MAX2383
for optimum linearity and return loss. It is important to tune the interstage matching network components along with the driver output matching components, to achieve the desired cascaded ACPR performance from the whole device.
Pin Configuration
TOP VIEW
Layout Issues
For best performance, pay attention to power-supply issues as well as to the layout of the signal lines. The EV kit can be used as a layout example. Ground connections followed by supply bypass are the most important.
A
LO+ / LO_EN
VCC
DROUT
GND
B
LO- / SHDN
MAX2383
GC
DRIN
Power-Supply and SHDN Bypassing
Bypass VCC with a 330pF capacitor to GND as close as possible to the V CC pin. Use separate vias to the ground plane for each of the bypass capacitors and minimize trace length to reduce inductance. Use three separate vias to the ground plane for each ground pin.
C IFINIFIN+ RFOUT GND
1
2
3
4
Power-Supply Layout
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration with a large decoupling capacitor at a central V CC node. The V CC traces branch out from this central node, each going to a separate VCC node in the PC board. At the end of each trace is a bypass capacitor that has low ESR at the RF frequency of operation. This arrangement provides local decoupling at each VCC pin. At high frequencies, any signal leaking out of one supply pin sees a relatively high impedance (formed by the VCC trace inductance) to the central VCC node, and an even higher impedance to any other supply pin, as well as a low impedance to ground through the bypass capacitor.
UCSP Reliability
The chip-scale package (UCSP) represents a unique package that greatly reduces board space compared to other packages. UCSP reliability is integrally linked to the user's assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP. This form factor may not perform equally to a packaged product through traditional mechanical reliability tests. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP. UCSP solder joint contact integrity must be considered since the package is attached through direct solder contact to the user's PC board. Testing done to characterize the UCSP reliability performance shows that it is capable of performing reliably through environmental stresses. Results of environmental stress tests and additional usage data and recommendations are detailed in the UCSP application note, which can be found on Maxim's website, www.maxim-ic.com.
Impedance-Matching Network Layout
The DROUT and interstage matching networks are very sensitive to layout-related parasitic. To minimize parasitic inductance, keep all traces short and place components as close as possible to the chip. To minimize parasitic capacitance, minimize the area of the plane.
Chip Information
TRANSISTOR COUNT: 998
6
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W-CDMA Upconverter and PA Driver with Power Control
Typical Operating Circuit
POUT VCC
MAX2383
LO_EN LO+ / LO_EN A1 VCC A2 DROUT A3 GND A4 PA DRVR GC B3
VCO
MAX2383
LOSHDN B1
B4 DRIN
SHDN C1 IFINC2 IFIN+ C3 RFOUT C4 GND
IF SAW FILTER
VCC
CASCADED; NO INTERSTAGE FILTER REQUIRED
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W-CDMA Upconverter and PA Driver with Power Control MAX2383
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12L UCSP 4x3, B12-5 .EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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